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DDECS
2009
IEEE
202views Hardware» more  DDECS 2009»
14 years 3 months ago
Asynchronous two-level logic of reduced cost
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
Igor Lemberski, Petr Fiser
ATAL
2007
Springer
14 years 3 months ago
A temporal epistemic logic with a reset operation
We present an axiomatisation for an extension of a temporal epistemic logic with an epistemic “reset” operator defined on the intersection between epistemic and temporal rela...
Alessio Lomuscio, Bozena Wozna
LPNMR
1999
Springer
14 years 1 months ago
A Comparison of Sceptical NAF-Free Logic Programming Approaches
Recently there has been increased interest in logic programming-based default reasoning approaches which are not using negation-as-failure in their object language. Instead, defau...
Grigoris Antoniou, Michael J. Maher, David Billing...
AUSAI
2005
Springer
14 years 2 months ago
Model Checking Sum and Product
We model the well-known Sum-and-Product problem in a modal logic, and verify its solution in a model checker. The modal logic is public announcement logic. The riddle is then imple...
Hans P. van Ditmarsch, Ji Ruan, L. C. Verbrugge
CADE
2004
Springer
14 years 9 months ago
A Machine-Checked Formalization of the Generic Model and the Random Oracle Model
Gilles Barthe, Jan Cederquist, Sabrina Tarento