Sciweavers

4737 search results - page 862 / 948
» The LOGIC negotiation model
Sort
View
ISCAS
2005
IEEE
224views Hardware» more  ISCAS 2005»
15 years 10 months ago
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga
ISQED
2005
IEEE
133views Hardware» more  ISQED 2005»
15 years 10 months ago
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao ...
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
15 years 10 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
ACMMSP
2005
ACM
115views Hardware» more  ACMMSP 2005»
15 years 10 months ago
Performance characteristics of MAUI: an intelligent memory system architecture
Combining ideas from several previous proposals, such as Active Pages, DIVA, and ULMT, we present the Memory Arithmetic Unit and Interface (MAUI) architecture. Because the “inte...
Justin Teller, Charles B. Silio Jr., Bruce L. Jaco...
MINENET
2005
ACM
15 years 10 months ago
Shrink: a tool for failure diagnosis in IP networks
Faults in an IP network have various causes such as the failure of one or more routers at the IP layer, fiber-cuts, failure of physical elements at the optical layer, or extraneo...
Srikanth Kandula, Dina Katabi, Jean-Philippe Vasse...