41 search results - page 4 / 9 » The Latency Hiding Effectiveness of Decoupled Access Execute... |
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
DSD
2002
IEEE
14 years 9 days ago
2002
IEEE
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done ...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
ASPLOS
1992
ACM
13 years 11 months ago
1992
ACM
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...