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FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
14 years 1 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...
BROADNETS
2004
IEEE
14 years 28 days ago
A Scalable Algorithm for Survivable Routing in IP-Over-WDM Networks
In IP-over-WDM networks, a logical IP network has to be routed on top of a physical optical fiber network. An important challenge hereby is to make the routing survivable. We call...
Frederick Ducatelle, Luca Maria Gambardella
VLDB
1995
ACM
66views Database» more  VLDB 1995»
14 years 22 days ago
A Performance Evaluation of OID Mapping Techniques
In this paper, three techniques to implement logical OIDs are thoroughly evaluated: hashing, B-trees and a technique called direct mapping. Among these three techniques, direct ma...
André Eickler, Carsten Andreas Gerlhof, Don...
AISB
2008
Springer
13 years 11 months ago
Substitution for Fraenkel-Mostowski foundations
Abstract. A fundamental and unanalysed logical concept is substitution. This seemingly innocuous operation -- substituting a variable for a term or valuating a variable to an eleme...
Murdoch Gabbay, Michael Gabbay
DFT
2008
IEEE
151views VLSI» more  DFT 2008»
13 years 11 months ago
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris...