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TACAS
2005
Springer
124views Algorithms» more  TACAS 2005»
14 years 2 months ago
Dynamic Symmetry Reduction
Abstract. Symmetry reduction is a technique to combat the state explosion problem in temporal logic model checking. Its use with symbolic representation has suffered from the proh...
E. Allen Emerson, Thomas Wahl
ECAI
2004
Springer
14 years 2 months ago
An Argumentative Approach to Assessing Natural Language Usage based on the Web Corpus
Abstract. In spite of the significant evolution of spelling and grammar checkers for word-processing software, the problem of judging the appropriateness of language usage in diff...
Carlos Iván Chesñevar, Ana Gabriela ...
ISQED
2003
IEEE
147views Hardware» more  ISQED 2003»
14 years 2 months ago
On Structural vs. Functional Testing for Delay Faults
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li...
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
14 years 2 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
14 years 2 months ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...