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» The Logical Execution Time Paradigm
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VTS
2002
IEEE
138views Hardware» more  VTS 2002»
14 years 1 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
EUROMICRO
1999
IEEE
14 years 1 months ago
Design Space Exploration in System Level Synthesis under Memory Constraints
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...
Radoslaw Szymanek, Krzysztof Kuchcinski
CONCUR
1990
Springer
14 years 29 days ago
A Temporal Calculus of Communicating Systems
In this paper we describe the calculus TCCS, an extension of the process algebra CCS with temporal constructs. The calculus is useful for the formal analysis of the timing aspects...
Faron Moller, Chris M. N. Tofts
ASPDAC
2007
ACM
80views Hardware» more  ASPDAC 2007»
14 years 27 days ago
Recognition of Fanout-free Functions
Factoring is a logic minimization technique to represent a Boolean function in an equivalent function with minimum literals. When realizing the circuit, a function represented in ...
Tsung-Lin Lee, Chun-Yao Wang
LISA
2007
13 years 11 months ago
Network Patterns in Cfengine and Scalable Data Aggregation
Network patterns are based on generic algorithms that execute on tree-based overlays. A set of such patterns has been developed at KTH to support distributed monitoring in network...
Mark Burgess, Matthew Disney, Rolf Stadler