456 search results - page 76 / 92 » The Logical Execution Time Paradigm |
ARITH
2005
IEEE
14 years 3 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
IEEEPACT
2005
IEEE
14 years 3 months ago
2005
IEEE
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topo...
VLDB
2004
ACM
14 years 3 months ago
2004
ACM
SQL in the IBM® DB2® Universal Database™ for Linux®, UNIX®, and Windows® (DB2 UDB) database management product has been extended to support nested INSERT, UPDATE, and DELET...
FCCM
2002
IEEE
14 years 2 months ago
2002
IEEE
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...