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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
CIKM
2007
Springer
14 years 2 months ago
Shine: search heterogeneous interrelated entities
Heterogeneous entities or objects are very common and are usually interrelated with each other in many scenarios. For example, typical Web search activities involve multiple types...
Xuanhui Wang, Jian-Tao Sun, Zheng Chen
BROADNETS
2005
IEEE
14 years 1 months ago
Modeling and performance evaluation of ISCSI storage area networks
Abstract— This paper provides a concise modeling and performance evaluation of the iSCSI storage area network (SAN) architecture and protocol. SANs play a key role in business co...
Christoph M. Gauger, Martin Köhn, Sebastian G...
OTM
2005
Springer
14 years 1 months ago
Spatio-temporal Schema Integration with Validation: A Practical Approach
We propose to enhance a schema integration process with a validation phase employing logic-based data models. In our methodology, we validate the source schemas against the data mo...
Anastasiya Sotnykova, Nadine Cullot, Christelle Va...
VRCAI
2004
ACM
14 years 1 months ago
Explorative construction of virtual worlds: an interactive kernel approach
Despite steady research advances in many aspects of virtual reality, building and testing virtual worlds remains to be a very difficult process. Most virtual environments are stil...
Jinseok Seo, Gerard Jounghyun Kim