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TCAD
2010
105views more  TCAD 2010»
13 years 3 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
TCAD
2010
133views more  TCAD 2010»
13 years 3 months ago
Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization
Protein crystallization is a commonly used technique for protein analysis and subsequent drug design. It predicts the 3-D arrangement of the constituent amino acids, which in turn ...
Tao Xu, Krishnendu Chakrabarty, Vamsee K. Pamula
TCAD
2010
110views more  TCAD 2010»
13 years 3 months ago
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Ha...
TCAD
2010
168views more  TCAD 2010»
13 years 3 months ago
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
Hoeseok Yang, Sungchan Kim, Soonhoi Ha
TCAD
2010
90views more  TCAD 2010»
13 years 3 months ago
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration
The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
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