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CHES
2009
Springer
200views Cryptology» more  CHES 2009»
14 years 8 months ago
Accelerating AES with Vector Permute Instructions
We demonstrate new techniques to speed up the Rijndael (AES) block cipher using vector permute instructions. Because these techniques avoid data- and key-dependent branches and mem...
Mike Hamburg
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
13 years 11 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
13 years 12 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie
ICML
1995
IEEE
14 years 8 months ago
Learning by Observation and Practice: An Incremental Approach for Planning Operator Acquisition
This paper describes an approach to automatically learn planning operators by observing expert solution traces and to further refine the operators through practice in a learning-b...
Xuemei Wang
DSN
2004
IEEE
13 years 11 months ago
An Architectural Framework for Providing Reliability and Security Support
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...