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IWMM
2000
Springer
137views Hardware» more  IWMM 2000»
14 years 12 days ago
Cycles to Recycle: Garbage Collection on the IA-64
The IA-64, Intel's 64-bit instruction set architecture, exhibits a number of interesting architectural features. Here we consider those features as they relate to supporting ...
Richard L. Hudson, J. Eliot B. Moss, Sreenivas Sub...
DAGSTUHL
2004
13 years 10 months ago
The Kiel Esterel Processor - A Semi-Custom, Configurable Reactive Processor
The synchronous language Esterel is an established language for developing reactive systems. It gives an abstract, well-defined and executable description of the application, and c...
Xin Li, Reinhard von Hanxleden
ASPLOS
1992
ACM
14 years 28 days ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
DAGSTUHL
2001
13 years 10 months ago
Understanding Algorithms by Means of Visualized Path Testing
Visualization of an algorithm offers only a rough picture of operations. Explanations are crucial for deeper understanding, because they help the viewer to associate the visualiza...
Ari Korhonen, Erkki Sutinen, Jorma Tarhio
CORR
2010
Springer
198views Education» more  CORR 2010»
13 years 9 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka