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CAV
1998
Springer
175views Hardware» more  CAV 1998»
14 years 1 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
EUROSYS
2010
ACM
14 years 1 months ago
Defeating return-oriented rootkits with "Return-Less" kernels
Targeting the operating system (OS) kernels, kernel rootkits pose a formidable threat to computer systems and their users. Recent efforts have made significant progress in blocki...
Jinku Li, Zhi Wang, Xuxian Jiang, Michael C. Grace...
CASES
2005
ACM
13 years 10 months ago
Hardware support for code integrity in embedded processors
Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increa...
Milena Milenkovic, Aleksandar Milenkovic, Emil Jov...
OSDI
2008
ACM
14 years 9 months ago
Binary Translation Using Peephole Superoptimizers
We present a new scheme for performing binary translation that produces code comparable to or better than existing binary translators with much less engineering effort. Instead of...
Sorav Bansal, Alex Aiken
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
14 years 5 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...