314 search results - page 43 / 63 » The Nachos Instructional Operating System |
EUROSYS
2010
ACM
14 years 5 months ago
2010
ACM
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
JPDC
2000
13 years 8 months ago
2000
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
CADE
1998
Springer
14 years 1 months ago
1998
Springer
Abstract. We present the first implementation of a theorem prover running on a smart card. The prover is written in Java and implements a dual tableau calculus. Due to the limited ...
ISPASS
2010
IEEE
14 years 3 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
ASPLOS
2010
ACM
14 years 3 months ago
2010
ACM
This paper introduces a new abstraction to accelerate the readbarriers and write-barriers used by language runtime systems. We exploit the fact that, dynamically, many barrier exe...