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CODES
2006
IEEE
14 years 1 months ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu
DFT
2006
IEEE
130views VLSI» more  DFT 2006»
14 years 1 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
ECRTS
2006
IEEE
14 years 1 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
GMP
2006
IEEE
127views Solid Modeling» more  GMP 2006»
14 years 1 months ago
Finding All Undercut-Free Parting Directions for Extrusions
For molding and casting processes, geometries that have undercut-free parting directions (UFPDs) are preferred for manufacturing. Identifying all UFPDs for arbitrary geometries at ...
Xiaorui Chen, Sara McMains
ICRA
2006
IEEE
110views Robotics» more  ICRA 2006»
14 years 1 months ago
Speeding-up Rao-blackwellized SLAM
— Recently, Rao-Blackwellized particle filters have become a popular tool to solve the simultaneous localization and mapping problem. This technique applies a particle filter i...
Giorgio Grisetti, Gian Diego Tipaldi, Cyrill Stach...