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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 28 days ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ACMDIS
2010
ACM
13 years 7 months ago
A tale of two publics: democratizing design at the margins
The design and use of Information and Communication Technology (ICT) has now evolved beyond its workplace origins to the wider public, expanding to people who live at the margins ...
Christopher A. Le Dantec, Jim Christensen, Mark Ba...
VISUALIZATION
2003
IEEE
14 years 27 days ago
Planet-Sized Batched Dynamic Adaptive Meshes (P-BDAM)
We describe an efficient technique for out-of-core management and interactive rendering of planet sized textured terrain surfaces. The technique, called P-Batched Dynamic Adaptiv...
Paolo Cignoni, Fabio Ganovelli, Enrico Gobbetti, F...
DAC
1995
ACM
13 years 11 months ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
SENSYS
2003
ACM
14 years 26 days ago
SIA: secure information aggregation in sensor networks
Sensor networks promise viable solutions to many monitoring problems. However, the practical deployment of sensor networks faces many challenges imposed by real-world demands. Sen...
Bartosz Przydatek, Dawn Xiaodong Song, Adrian Perr...