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» The Optimal Virtual Path Design of ATM Networks
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DAC
2005
ACM
14 years 8 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
MSS
2003
IEEE
173views Hardware» more  MSS 2003»
14 years 1 months ago
Peabody: The Time Travelling Disk
Disk drives are now available with capacities on the order of hundreds of gigabytes. What has not become available is an easy way to manage storage. With installed machines locate...
Charles B. Morrey III, Dirk Grunwald
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 1 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
INFOCOM
2006
IEEE
14 years 1 months ago
Minimum User-Perceived Interference Routing in Service Composition
— Service Composition is a promising technology for providing on-demand services in dynamic and loosely coupled peerto-peer (P2P) networks. Because of system dynamics, such as th...
Li Xiao, Klara Nahrstedt
FITRAMEN
2008
13 years 9 months ago
A Fair and Dynamic Load-Balancing Mechanism
The current data network scenario makes Traffic Engineering (TE) a very challenging task. The ever growing access rates and new applications running on end-hosts result in more var...
Federico Larroca, Jean-Louis Rougier