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IEEEPACT
2008
IEEE
14 years 4 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
HPDC
2007
IEEE
14 years 4 months ago
A fast topology inference: a building block for network-aware parallel processing
Adapting to the network is the key to achieving high performance for communication-intensive applications, including scientific computing, data intensive computing, and multicast...
Tatsuya Shirai, Hideo Saito, Kenjiro Taura
INFOCOM
2007
IEEE
14 years 4 months ago
A Cross-Layer Architecture to Exploit Multi-Channel Diversity with a Single Transceiver
—The design of multi-channel multi-hop wireless mesh networks is centered around the way nodes synchronize when they need to communicate. However, existing designs are confined ...
Jay A. Patel, Haiyun Luo, Indranil Gupta
CCECE
2006
IEEE
14 years 3 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
MOBICOM
2003
ACM
14 years 3 months ago
ARC: an integrated admission and rate control framework for CDMA data networks based on non-cooperative games
The competition among wireless data service providers brings in an option for the customers to switch their providers, due to unsatisfactory service or otherwise. However, the exi...
Haitao Lin, Mainak Chatterjee, Sajal K. Das, Kalya...