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HPCC
2009
Springer
14 years 1 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
CF
2008
ACM
13 years 10 months ago
DMA-based prefetching for i/o-intensive workloads on the cell architecture
Recent advent of the asymmetric multi-core processors such as Cell Broadband Engine (Cell/BE) has popularized the use of heterogeneous architectures. A growing body of research is...
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Ni...
DAC
2009
ACM
14 years 1 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers
ASPDAC
2008
ACM
135views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Block cache for embedded systems
On chip memories provide fast and energy efficient storage for code and data in comparison to caches or external memories. We present techniques and algorithms that allow for an au...
Dominic Hillenbrand, Jörg Henkel
IEEEPACT
1999
IEEE
14 years 26 days ago
Memory System Support for Image Processing
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...
Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sall...