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IEEEPACT
2006
IEEE
14 years 2 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
SIGMETRICS
1997
ACM
117views Hardware» more  SIGMETRICS 1997»
14 years 23 days ago
Informed Multi-Process Prefetching and Caching
Informed prefetching and caching based on application disclosure of future I/O accesses (hints) can dramatically reduce the execution time of I/O-intensive applications. A recent ...
Andrew Tomkins, R. Hugo Patterson, Garth A. Gibson
IPPS
1998
IEEE
14 years 25 days ago
Design and Implementation of a Parallel I/O Runtime System for Irregular Applications
In this paper we present the design, implementation and evaluation of a runtime system based on collective I/O techniques for irregular applications. We present two models, namely...
Jaechun No, Sung-Soon Park, Jesús Carretero...
MICRO
2003
IEEE
135views Hardware» more  MICRO 2003»
14 years 1 months ago
Generational Cache Management of Code Traces in Dynamic Optimization Systems
A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...
Kim M. Hazelwood, Michael D. Smith
IISWC
2008
IEEE
14 years 3 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood