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HICSS
2008
IEEE
156views Biometrics» more  HICSS 2008»
14 years 4 months ago
A Centrality Measure for Electrical Networks
—We derive a measure of “electrical centrality” for AC power networks, which describes the structure of the network as a function of its electrical topology rather than its p...
Paul Hines, Seth Blumsack
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
14 years 4 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
KES
1999
Springer
14 years 2 months ago
Dynamic Demes parallel genetic algorithm
Abstract—Dynamic Demes is a new method for the parallelisation of evolutionary algorithms. It was derived as a combination of two other parallelisation algorithms: the master-sla...
Mariusz Nowostawski, Riccardo Poli
GLVLSI
2005
IEEE
144views VLSI» more  GLVLSI 2005»
14 years 3 months ago
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
—On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply ...
Mikhail Popovich, Eby G. Friedman, Michael Sotman,...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 7 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha