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PATMOS
2010
Springer
13 years 5 months ago
L1 Data Cache Power Reduction Using a Forwarding Predictor
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
P. Carazo, R. Apolloni, Fernando Castro, Daniel Ch...
SOCC
2008
IEEE
106views Education» more  SOCC 2008»
14 years 1 months ago
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With s...
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
NOMS
2010
IEEE
204views Communications» more  NOMS 2010»
13 years 5 months ago
Integrated management of application performance, power and cooling in data centers
Abstract—Data centers contain IT, power and cooling infrastructures, each of which is typically managed independently. In this paper, we propose a holistic approach that couples ...
Yuan Chen, Daniel Gmach, Chris Hyser, Zhikui Wang,...
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 11 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ARITH
2005
IEEE
14 years 1 months ago
Data Dependent Power Use in Multipliers
Recent research has demonstrated the vulnerability of certain smart card architectures to power and electromagnetic analysis when multiplier operations are insufficiently shielde...
Colin D. Walter, David Samyde