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» The Power of Hybrid Acceleration
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STTT
2008
88views more  STTT 2008»
13 years 8 months ago
PHAVer: algorithmic verification of hybrid systems past HyTech
In 1995, HyTech broke new ground as a potentially powerful tool for verifying hybrid systems
Goran Frehse
VLSID
2008
IEEE
133views VLSI» more  VLSID 2008»
14 years 9 months ago
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
HPCA
2009
IEEE
14 years 9 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
14 years 2 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 5 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks