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» The Power of the Middle Bit
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GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
14 years 1 months ago
CMOS flash analog-to-digital converter for high speed and low voltage applications
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flas...
Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi
APCCAS
2006
IEEE
224views Hardware» more  APCCAS 2006»
13 years 10 months ago
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment
Abstract-- Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory pl...
Masanori Hariyama, Michitaka Kameyama
INFOCOM
2010
IEEE
13 years 6 months ago
Joint Power and Secret Key Queue Management for Delay Limited Secure Communication
—In recent years, the famous wiretap channel has been revisited by many researchers and information theoretic secrecy has become an active area of research in this setting. In th...
Onur Güngör 0002, Jian Tan, Can Emre Kok...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
14 years 1 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
PIMRC
2010
IEEE
13 years 5 months ago
Bit-power loading algorithms based on Effective SINR Mapping techniques
Bit-Power Loading (BPL) algorithms are proposed based on Effective SINR Mapping (ESM) techniques. The ESM techniques used are the Exponential ESM (EESM) as well as the Mean Mutual ...
Ioannis Dagres, Natalia Miliou, Andreas Zalonis, A...