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DATE
2003
IEEE
151views Hardware» more  DATE 2003»
15 years 11 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
ICMCS
2000
IEEE
63views Multimedia» more  ICMCS 2000»
15 years 10 months ago
Unifying Conversational Multimedia Interfaces for Accessing Network Services Across Communication Devices
This paper investigates architecture and interface design issues in engineering conversational multimedia interfaces for accessing network-based services. In particular, we focus ...
Giuseppe Di Fabbrizio, S. Narayanan, P. Ruscitti, ...
157
Voted
LCN
2005
IEEE
15 years 11 months ago
Network Management Challenges for Next Generation Networks
Generally, current network management technologies follow two approaches: ITU-T’s recommendations for Telecommunication Management Network (TMN) and IETF’s Simple Network Mana...
Mo Li, Kumbesan Sandrasegaran
MOBICOM
2006
ACM
16 years 2 days ago
State-of-the-art in protocol research for underwater acoustic sensor networks
In this paper, architectures for two-dimensional and three-dimensional underwater sensor networks are discussed. A detailed overview on the current solutions for medium access con...
Ian F. Akyildiz, Dario Pompili, Tommaso Melodia
170
Voted
ICES
2005
Springer
195views Hardware» more  ICES 2005»
15 years 11 months ago
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs
A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on t...
Jan Korenek, Lukás Sekanina