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DATE
2007
IEEE
97views Hardware» more  DATE 2007»
14 years 3 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
TVLSI
2008
92views more  TVLSI 2008»
13 years 8 months ago
Reconfigurable Architecture for Network Flow Analysis
This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high networ...
Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker D...
TON
2008
75views more  TON 2008»
13 years 8 months ago
TVA: a DoS-limiting network architecture
We motivate the capability approach to network denial-of-service (DoS) attacks, and evaluate the TVA architecture which builds on capabilities. With our approach, rather than send ...
Xiaowei Yang, David Wetherall, Thomas E. Anderson
MONET
2008
150views more  MONET 2008»
13 years 8 months ago
A Multi-radio 802.11 Mesh Network Architecture
Routers equipped with multiple 802.11 radios can alleviate capacity problems in wireless mesh networks. However, a practical, complete system architecture that can realize the bene...
Krishna N. Ramachandran, Irfan Sheriff, Elizabeth ...
HPCA
2011
IEEE
13 years 19 days ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan