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» The Size of Power Automata
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TCAD
2008
172views more  TCAD 2008»
13 years 8 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
FCT
2009
Springer
14 years 3 months ago
Alternating Weighted Automata
Weighted automata are finite automata with numerical weights on transitions. Nondeterministic weighted automata define quantitative languages L that assign to each word w a real ...
Krishnendu Chatterjee, Laurent Doyen, Thomas A. He...
ISCAS
1999
IEEE
77views Hardware» more  ISCAS 1999»
14 years 22 days ago
Power reduction through iterative gate sizing and voltage scaling
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, W...
DAC
2005
ACM
13 years 10 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
BMCBI
2010
80views more  BMCBI 2010»
13 years 8 months ago
Power and sample size estimation in microarray studies
Background: Before conducting a microarray experiment, one important issue that needs to be determined is the number of arrays required in order to have adequate power to identify...
Wei-Jiun Lin, Huey-miin Hsueh, James J. Chen