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» The Size of Power Automata
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HPCA
2011
IEEE
12 years 11 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
12 years 11 months ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
PDP
2011
IEEE
12 years 11 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
CORR
2012
Springer
230views Education» more  CORR 2012»
12 years 3 months ago
RT-SLAM: A Generic and Real-Time Visual SLAM Implementation
Abstract. This article presents a new open-source C++ implementation to solve the SLAM problem, which is focused on genericity, versatility and high execution speed. It is based on...
Cyril Roussillon, Aurélien Gonzalez, Joan S...
POPL
2012
ACM
12 years 2 months ago
Playing in the grey area of proofs
Interpolation is an important technique in verification and static analysis of programs. In particular, interpolants extracted from proofs of various properties are used in invar...
Krystof Hoder, Laura Kovács, Andrei Voronko...