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126
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IPPS
2006
IEEE
15 years 9 months ago
Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications
Recently, under a fixed power budget, asymmetric multiprocessors (AMP) have been proposed to improve the performance of multi-threaded applications compared to symmetric multiproc...
Ryan E. Grant, Ahmad Afsahi
134
Voted
IPPS
2006
IEEE
15 years 9 months ago
Dynamically reconfigurable cache architecture using adaptive block allocation policy
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
Milene Barbosa Carvalho, Luís Fabríc...
136
Voted
IPPS
2006
IEEE
15 years 9 months ago
Coterminous locality and coterminous group data prefetching on chip-multiprocessors
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...
Xudong Shi, Zhen Yang, Jih-Kwon Peir, Lu Peng, Yen...
115
Voted
ISCA
2006
IEEE
138views Hardware» more  ISCA 2006»
15 years 9 months ago
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs
We present Program Demultiplexing (PD), an execution paradigm that creates concurrency in sequential programs by "demultiplexing" methods (functions or subroutines). Cal...
Saisanthosh Balakrishnan, Gurindar S. Sohi
125
Voted
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
15 years 9 months ago
Improving Cost, Performance, and Security of Memory Encryption and Authentication
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
Chenyu Yan, Daniel Englender, Milos Prvulovic, Bri...