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CF
2010
ACM
14 years 13 days ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
ISCA
2007
IEEE
168views Hardware» more  ISCA 2007»
14 years 1 months ago
Limiting the power consumption of main memory
The peak power consumption of hardware components affects their power supply, packaging, and cooling requirements. When the peak power consumption is high, the hardware components...
Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Me...
ASE
2006
110views more  ASE 2006»
13 years 7 months ago
Runtime recovery and manipulation of software architecture of component-based systems
Recently, more attention is paid to the researches and practices on how to use software architecture in software maintenance and evolution to reduce their complexity and cost. The ...
Gang Huang, Hong Mei, Fuqing Yang
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 2 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
VTC
2008
IEEE
113views Communications» more  VTC 2008»
14 years 1 months ago
Non-Linear UWB Receivers with MLSE Post-Detection
— A wireless body area network with an average throughput of 500 kbps is considered based on ultra-wideband (UWB) pulse position modulation. For a long battery autonomy ultra low...
Florian Troesch, Thomas Zasowski, Armin Wittneben