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ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 4 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
14 years 4 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
14 years 4 months ago
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederi...
WADS
2009
Springer
291views Algorithms» more  WADS 2009»
14 years 4 months ago
On the Power of the Semi-Separated Pair Decomposition
Abstract. A Semi-Separated Pair Decomposition (SSPD), with parameter s > 1, of a set S ⊂ Rd is a set {(Ai, Bi)} of pairs of subsets of S such that for each i, there are balls ...
Mohammad Ali Abam, Paz Carmi, Mohammad Farshi, Mic...
ARCS
2009
Springer
14 years 4 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
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