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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
CONCURRENCY
2006
77views more  CONCURRENCY 2006»
13 years 7 months ago
Revocation techniques for Java concurrency
er proposes two approaches to managing concurrency in Java using a guarded region abstraction. Both approaches use revocation of such regions
Adam Welc, Suresh Jagannathan, Antony L. Hosking
ICIA
2007
13 years 10 months ago
Intent Recognition for Human-Robot Interaction
Effective human-robot cooperation requires robotic devices that understand human goals and intentions. We frame the problem of intent recognition as one of tracking and predicting...
Andreas G. Hofmann, Brian C. Williams
ESWS
2010
Springer
14 years 14 days ago
Guarding a Walled Garden - Semantic Privacy Preferences for the Social Web
Abstract. With increasing usage of Social Networks, giving users the possibility to establish access restrictions on their data and resources becomes more and more important. Howev...
Philipp Kärger, Wolf Siberski
FSTTCS
2010
Springer
13 years 5 months ago
Two Size Measures for Timed Languages
Quantitative properties of timed regular languages, such as information content (growth rate, entropy) are explored. The approach suggested by the same authors is extended to lang...
Eugene Asarin, Aldric Degorre