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DATE
2006
IEEE
119views Hardware» more  DATE 2006»
15 years 10 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
DMIN
2006
111views Data Mining» more  DMIN 2006»
15 years 5 months ago
Research on Classification of Printing Fault Using Support Vector Machines
: For the characteristics of malfunction diagnose system a model to classify fault printing based on support vector machines is discussed. The printing malfunctions have many class...
Ye-Li Li, Ya-Li Qi
SCAM
2006
IEEE
15 years 10 months ago
Bug Classification Using Program Slicing Metrics
In this paper, we introduce 13 program slicing metrics for C language programs. These metrics use program slice information to measure the size, complexity, coupling, and cohesion...
Kai Pan, Sunghun Kim, E. James Whitehead Jr.
RECONFIG
2009
IEEE
165views VLSI» more  RECONFIG 2009»
15 years 11 months ago
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
Muhammad Aqeel Wahlah, Kees G. W. Goossens
ISSRE
2007
IEEE
15 years 6 months ago
Using Machine Learning to Support Debugging with Tarantula
Using a specific machine learning technique, this paper proposes a way to identify suspicious statements during debugging. The technique is based on principles similar to Tarantul...
Lionel C. Briand, Yvan Labiche, Xuetao Liu