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    » The Wave Pipeline Effect on LUT-Based FPGA Architectures
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    FPGA
    1999
    ACM
    132views FPGA» more  FPGA 1999»
    The Wave Pipeline Effect on LUT-Based FPGA Architectures
    14 years 3 months ago
    The Wave Pipeline Effect on LUT-Based FPGA Architectures
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    André DeHon
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    CF
    2004
    ACM
    131views Applied Computing» more  CF 2004»
    Fault tolerant clockless wave pipeline design
    14 years 4 months ago
    Fault tolerant clockless wave pipeline design
    Download  www.ece.neu.edu
    This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
    T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...
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    FPGA
    1999
    ACM
    174views FPGA» more  FPGA 1999»
    Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
    14 years 3 months ago
    Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
    Download  www.cecs.uci.edu
    Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
    Peter Kollig, Bashir M. Al-Hashimi
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    FPGA
    1997
    ACM
    149views FPGA» more  FPGA 1997»
    Signal Processing at 250 MHz Using High-Performance FPGA's
    14 years 3 months ago
    Signal Processing at 250 MHz Using High-Performance FPGA's
    Download  www.fpga.com
    This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
    Brian Von Herzen
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    FPGA
    2004
    ACM
    145views FPGA» more  FPGA 2004»
    Exploration of pipelined FPGA interconnect structures
    14 years 4 months ago
    Exploration of pipelined FPGA interconnect structures
    Download  www.ece.wisc.edu
    In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
    Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
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