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APCCAS
2006
IEEE
271views Hardware» more  APCCAS 2006»
14 years 2 months ago
Fully-multiplexed First-order 3D IIR Frequency-Planar Filter Module
— A VLSI hardware architecture for the on-chip implementation of a first-order 3D IIR fully-multiplexed frequencyplanar filter module (FMFPM) is proposed. FMFPMs may be employed ...
Arjuna Madanayake, Leonard T. Bruton
AVSS
2006
IEEE
14 years 2 months ago
Real-Time Video Segmentation with VGA Resolution and Memory Bandwidth Reduction
This paper presents the implementation of a video segmentation unit used for embedded automated video surveillance systems. Various aspects of the underlying segmentation algorith...
Hongtu Jiang, Viktor Öwall, Håkan Ard&o...
DELTA
2006
IEEE
14 years 2 months ago
A Hardware Implementation of Layer 2 MPLS
This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and impro...
Raymond Peterkin, Dan Ionescu
GLOBECOM
2006
IEEE
14 years 2 months ago
Noise Model Analysis of Optimized Mixed-Radix Structures for Pulsed OFDM
Pulsed OFDM (P-OFDM) is a proposed enhancement to Multi-Band Orthogonal Frequency Division Multiplexing which reduces the power and complexity of Ultra Wideband transceivers witho...
Kai-Chuan Chang, Gerald E. Sobelman
IPPS
2006
IEEE
14 years 2 months ago
Securing embedded programmable gate arrays in secure circuits
The purpose of this article is to propose a survey of possible approaches for implementing embedded reconfigurable gate arrays into secure circuits. A standard secure interfacing ...
Nicolas Valette, Lionel Torres, Gilles Sassatelli,...