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CASES
2004
ACM
14 years 25 days ago
Procedure placement using temporal-ordering information: dealing with code size expansion
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
Christophe Guillon, Fabrice Rastello, Thierry Bida...
IWNAS
2008
IEEE
14 years 1 months ago
Software Barrier Performance on Dual Quad-Core Opterons
Multi-core processors based SMP servers have become building blocks for Linux clusters in recent years because they can deliver better performance for multi-threaded programs thro...
Jie Chen, William A. Watson III
WOSP
2004
ACM
14 years 24 days ago
Collecting whole-system reference traces of multiprogrammed and multithreaded workloads
The simulated evaluation of memory management policies relies on reference traces—logs of memory operations performed by running processes. No existing approach to reference tra...
Scott F. Kaplan
SPAA
1996
ACM
13 years 11 months ago
An Analysis of Dag-Consistent Distributed Shared-Memory Algorithms
In this paper, we analyze the performance of parallel multithreaded algorithms that use dag-consistent distributed shared memory. Specifically, we analyze execution time, page fau...
Robert D. Blumofe, Matteo Frigo, Christopher F. Jo...
SIGGRAPH
1997
ACM
13 years 11 months ago
Rendering complex scenes with memory-coherent ray tracing
Simulating realistic lighting and rendering complex scenes are usually considered separate problems with incompatible solutions. Accurate lighting calculations are typically perfo...
Matt Pharr, Craig E. Kolb, Reid Gershbein, Pat Han...