86 search results - page 11 / 18 » The complexity of verifying memory coherence |
ISCAPDCS
2004
13 years 10 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
ECOOP
1999
Springer
14 years 26 days ago
1999
Springer
Many Java programmers believe they do not have to worry about memory management because of automatic garbage collection. In fact, many Java programs run out of memory unexpectedly ...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
CRYPTO
2011
Springer
12 years 8 months ago
2011
Springer
We consider the problem of delegating computation, where the delegator doesn’t even know the input to the function being delegated, and runs in time significantly smaller than ...
POPL
2009
ACM
14 years 9 months ago
2009
ACM
Transactional memory (TM) is a promising paradigm for concurrent programming. Whereas the number of TM implementations is growing, however, little research has been conducted to p...