4266 search results - page 128 / 854 » The container loading problem |
119
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FPL
2009
Springer
15 years 7 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
104
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HPCA
1997
IEEE
15 years 6 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
128
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DSN
2006
IEEE
15 years 6 months ago
2006
IEEE
We construct, analyze and solve models of systems where a number of servers offer services to an incoming stream of demands. Each server goes through alternating periods of being ...
170
Voted
MICRO
1995
IEEE
15 years 6 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
131
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WSC
2008
15 years 4 months ago
2008
This research proposes the integration of a Geographic Information System (GIS) with the Arena Simulation software to model the transit of ocean-going vessels through the Panama C...