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FMCAD
2009
Springer
14 years 2 months ago
Scaling VLSI design debugging with interpolation
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
Brian Keng, Andreas G. Veneris
TLDI
2003
ACM
134views Formal Methods» more  TLDI 2003»
14 years 27 days ago
Scrap your boilerplate: a practical design pattern for generic programming
We describe a design pattern for writing programs that traverse data structures built from rich mutually-recursive data types. Such programs often have a great deal of “boilerpl...
Ralf Lämmel, Simon L. Peyton Jones
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 1 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
SBMF
2010
Springer
205views Formal Methods» more  SBMF 2010»
13 years 2 months ago
A High-Level Language for Modeling Algorithms and Their Properties
Designers of concurrent and distributed algorithms usually express them using pseudo-code. In contrast, most verification techniques are based on more mathematically-oriented forma...
Sabina Akhtar, Stephan Merz, Martin Quinson
UML
2004
Springer
14 years 1 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...