Sciweavers

2416 search results - page 410 / 484
» The design and implementation of typed scheme
Sort
View
FPGA
2012
ACM
300views FPGA» more  FPGA 2012»
12 years 3 months ago
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...
Yehdhih Ould Mohammed Moctar, Nithin George, Hadi ...
IPPS
2008
IEEE
14 years 2 months ago
SNAP, Small-world Network Analysis and Partitioning: An open-source parallel graph framework for the exploration of large-scale
We present SNAP (Small-world Network Analysis and Partitioning), an open-source graph framework for exploratory study and partitioning of large-scale networks. To illustrate the c...
David A. Bader, Kamesh Madduri
HPCA
1998
IEEE
13 years 12 months ago
Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
Scalable shared-memory multiprocessors that are designed as Cache-Only Memory Architectures Coma allow automatic replication and migration of data in the main memory. This enhance...
Sujoy Basu, Josep Torrellas
SIGCOMM
2010
ACM
13 years 7 months ago
Generic and automatic address configuration for data center networks
Data center networks encode locality and topology information into their server and switch addresses for performance and routing purposes. For this reason, the traditional address...
Kai Chen, Chuanxiong Guo, Haitao Wu, Jing Yuan, Zh...
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 7 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek