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» The design of a high performance low power microprocessor
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ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
14 years 2 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...
IWCMC
2006
ACM
14 years 2 months ago
Cross-layer performance analysis of joint rate and power adaptation schemes with multiple-user contention in Nakagami fading cha
Adaptively adjusting transmission rate and power to concurrently enhance goodput and save energy is an important issue in the wireless local area network (WLAN). However, goodput ...
Li-Chun Wang, Kuang-Nan Yen, Jane-Hwa Huang, Ander...
PERCOM
2010
ACM
14 years 25 days ago
Negotiate power and performance in the reality of RFID systems
—Recent years have witnessed the wide adoption of the RFID technology in many important application domains including logistics, inventory, retailing, public transportation, and ...
Xunteng Xu, Lin Gu, Jianping Wang, Guoliang Xing
ICCAD
2009
IEEE
93views Hardware» more  ICCAD 2009»
13 years 6 months ago
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. N...
Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Ch...
CORR
2008
Springer
127views Education» more  CORR 2008»
13 years 9 months ago
Achieving Near-Capacity at Low SNR on a Multiple-Antenna Multiple-User Channel
We analyze the sensitivity of the capacity of a multi-antenna multi-user system to the number of users being served. We show analytically that, for a given desired sum-rate, the e...
Chau Yuen, Bertrand M. Hochwald