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» The design of a high performance low power microprocessor
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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
14 years 13 days ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
EVOW
2000
Springer
14 years 15 days ago
Prediction of Power Requirements for High-Speed Circuits
Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from f...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 1 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
VTC
2007
IEEE
146views Communications» more  VTC 2007»
14 years 3 months ago
Orthogonal STBC in General Nakagami-m Fading Channels: BER Analysis and Optimal Power Allocation
Abstract— We analyze the performance of multiple-input multiple-output (MIMO) systems employing orthogonal space-time block codes (STBC) in general Nakagami-m fading channels wit...
Andreas Müller, Joachim Speidel
CODES
2009
IEEE
14 years 3 months ago
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redun...
Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles