517 search results - page 11 / 104 » The design of a low energy FPGA |
FPGA
2011
ACM
12 years 10 months ago
2011
ACM
As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...
OOPSLA
2010
Springer
13 years 5 months ago
2010
Springer
Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energyintensive operations in order to reduce overall energy consumption and i...
CSREAESA
2003
13 years 8 months ago
2003
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
14 years 8 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—Systems on Chip (SoCs) congregate multiple modules and advanced interconnection schemes, such as networks on chip (NoCs). One relevant problem in SoC design is module mapping on...