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» The design of a low energy FPGA
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INFOCOM
2011
IEEE
12 years 11 months ago
Networking low-power energy harvesting devices: Measurements and algorithms
—Recent advances in energy harvesting materials and ultra-low-power communications will soon enable the realization of networks composed of energy harvesting devices. These devic...
Maria Gorlatova, Aya Wallwater, Gil Zussman
CHES
2005
Springer
146views Cryptology» more  CHES 2005»
14 years 27 days ago
AES on FPGA from the Fastest to the Smallest
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
Tim Good, Mohammed Benaissa
ICCCN
2008
IEEE
14 years 1 months ago
Multi-Hop RFID Wake-Up Radio: Design, Evaluation and Energy Tradeoffs
Abstract—Energy efficiency is a central challenge in batteryoperated sensor networks. Current energy-efficient mechanisms employ either duty cycling, which reduces idle listeni...
Raja Jurdak, Antonio G. Ruzzelli, Gregory M. P. O'...
CDES
2006
240views Hardware» more  CDES 2006»
13 years 8 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
CODES
2001
IEEE
13 years 11 months ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue