72 search results - page 6 / 15 » The design of a low power asynchronous multiplier |
DSD
2002
IEEE
14 years 15 days ago
2002
IEEE
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...
VLSID
2007
IEEE
14 years 1 months ago
2007
IEEE
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
SBCCI
2009
ACM
14 years 6 days ago
2009
ACM
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
ARITH
2005
IEEE
14 years 1 months ago
2005
IEEE
The pipelined CORDIC with linear approximation to rotation has been proposed to achieve reductions in delay, power and area; however, the schemes for rotation (multiplication) and...