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IPPS
2005
IEEE
14 years 2 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss
IRI
2005
IEEE
14 years 2 months ago
Data-knowledge-context: an application model for collaborative work
For many years, researchers and software developers have been seeking to develop systems and applications to enable efficient and effective group work and organizational memory. ...
Lee A. Iverson
IWIA
2005
IEEE
14 years 2 months ago
Malware Defense Using Network Security Authentication
Malware defenses have primarily relied upon intrusion fingerprints to detect suspicious network behavior. While effective for discovering computers that are already compromised,...
Joseph V. Antrosio, Errin W. Fulp
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
14 years 2 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 2 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
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