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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
13 years 11 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
IPPS
1998
IEEE
14 years 3 months ago
Efficient Runtime Thread Management for the Nano-Threads Programming Model
Abstract. The nano-threads programming model was proposed to effectively integrate multiprogramming on shared-memory multiprocessors, with the exploitation of fine-grain parallelis...
Dimitrios S. Nikolopoulos, Eleftherios D. Polychro...
ICSM
2003
IEEE
14 years 4 months ago
Library Miniaturization Using Static and Dynamic Information
Moving to smaller libraries can be considered as a relevant task when porting software systems to limited-resource devices (e.g., hand-helds). Library miniaturization will be part...
Giuliano Antoniol, Massimiliano Di Penta
LREC
2008
170views Education» more  LREC 2008»
14 years 18 days ago
A Semantic Memory for Incremental Ontology Population
Generally, ontology learning and population is applied as a semi-automatic approach to knowledge acquisition in natural language understanding systems. That means, after the ontol...
Berenike Loos, Lasse Schwarten
WMPI
2004
ACM
14 years 4 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström