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    SBRN
    1998
    IEEE
    190views Neural Networks» more  SBRN 1998»
    Implementation of a Probabilistic Neural Network for Multi-spectral Image Classification on an FPGA based Custom Computing Machi
    14 years 2 months ago
    Implementation of a Probabilistic Neural Network for Multi-spectral Image Classification on an FPGA based Custom Computing Machi
    Download  fsweb.olin.edu
    As the demand for higher performance computers for the processing of remote sensing science algorithms increases, the need to investigate new computing paradigms is justified. Fie...
    Marco A. Figueiredo, Clay Gloster
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    DAC
    1997
    ACM
    160views Computer Architecture» more  DAC 1997»
    Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
    14 years 2 months ago
    Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
    Download  www.cecs.uci.edu
    The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
    Marleen Adé, Rudy Lauwereins, J. A. Peperst...
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    ELPUB
    2007
    ACM
    111views Information Technology» more  ELPUB 2007»
    A Lifeboat Doesn't Do You any Good if it's not There when You Need it: Open Access and its Place in the New Electronic Publishin
    14 years 1 months ago
    A Lifeboat Doesn't Do You any Good if it's not There when You Need it: Open Access and its Place in the New Electronic Publishin
    Download  elpub.scix.net
    This paper draws on the results of recent research into digital publishing in Latin America sponsored by the European Commission's ALFA programme. It outlines the growth in p...
    Ian M. Johnson
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    FCCM
    2009
    IEEE
    123views VLSI» more  FCCM 2009»
    Scalable High Throughput and Power Efficient IP-Lookup on FPGA
    14 years 1 months ago
    Scalable High Throughput and Power Efficient IP-Lookup on FPGA
    Download  halcyon.usc.edu
    Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
    Hoang Le, Viktor K. Prasanna
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    FPL
    2009
    Springer
    179views Hardware» more  FPL 2009»
    Building heterogeneous reconfigurable systems using threads
    14 years 1 months ago
    Building heterogeneous reconfigurable systems using threads
    Download  hthreads.csce.uark.edu
    Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
    Jason Agron, David L. Andrews
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