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RECONFIG
2009
IEEE
118views VLSI» more  RECONFIG 2009»
14 years 4 months ago
Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations
Abstract. Protecting an implementation against Side Channel Analysis for Reverse Engineering (SCARE) attacks is a great challenge and we address this challenge by presenting a fir...
Julien Bringer, Hervé Chabanne, Jean-Luc Da...
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 4 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
14 years 4 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
ICPP
2008
IEEE
14 years 4 months ago
VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
Heiner Litz, Holger Fröning, Mondrian Nü...
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 4 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...