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DAC
2009
ACM
14 years 8 months ago
Spare-cell-aware multilevel analytical placement
Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validatio...
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yu...
PDP
2006
IEEE
14 years 1 months ago
An Experimental Validation of the PRO Model for Parallel and Distributed Computation
— The Parallel Resource-Optimal (PRO) computation model was introduced by Gebremedhin et al. [2002] as a framework for the design and analysis of efficient parallel algorithms. ...
Mohamed Essaïdi, Jens Gustedt
ISAAC
2009
Springer
114views Algorithms» more  ISAAC 2009»
14 years 2 months ago
Good Programming in Transactional Memory
Abstract. In a multicore transactional memory (TM) system, concurrent execution threads interact and interfere with each other through shared memory. The less interference a progra...
Raphael Eidenbenz, Roger Wattenhofer
GECCO
2007
Springer
268views Optimization» more  GECCO 2007»
14 years 1 months ago
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
Joachim Becker, Stanis Trendelenburg, Fabian Henri...
FCCM
1999
IEEE
210views VLSI» more  FCCM 1999»
13 years 12 months ago
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results
Abstract We are developing an integrated algorithm analysis and mapping environment particularly tailored for signal processing applications on Adaptive Computing Systems ACS. Our ...
Eric K. Pauer, Paul D. Fiore, John M. Smith