Spare-cell-aware multilevel analytical placement

Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validation is the use of spare cells. In the literature, most existing works focus on developing new delicate spare cell structures. On the other hand, the placement of spare cells has a crucial impact on the design cycle and cost of the post-silicon debugging; however, there exists not much work on this placement problem. In this paper, we propose the first spare-cell-aware analytical placement framework which predicts the spare cell requirement and considers spare cell insertion during global placement. We also propose a multilevel spare cell insertion technique which provides a more efficient spare cell planning and a better control of quality impact due to spare cell insertion. To guide the selection of available spare cell positions during insertion, we propose a mixed-integer-linearprogramming formulation to det...

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao
• Keywords: DAC 2009, Design Automation, Multilevel Spare Cell, Spare Cell Insertion, Spare Cell Positions